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L9803 データシート(PDF) 98 Page - STMicroelectronics |
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L9803 データシート(HTML) 98 Page - STMicroelectronics |
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98 / 126 page  On-Chip Peripherals L9803 98/126 Note: The DIR signal is internally synchronized with the PWM1 and PWM2 signals according to the selected Driving Mode. After writing the DIR bit in BCSR register, the direction changes in correspondence with the first rising edge of PWM1. The same procedure is used in the case of PWM2. This allows the proper control of the direction changes. When the PWM signal is 0% or 100%, being no edges available, the DIR bit can’t be latched and the direction does not change until a PWM edge occurs. 1 1 0 0 0 1 0 1 0 1 BRAKE Full Bridge 1 1 0 1 0 1 1 0 0 1 FORWARD Full Bridge 1 1 1 0 0 1 0 1 0 1 BRAKE Full Bridge 1 1 1 1 0 1 0 1 1 0 BACK Full Bridge 1 1 0 0 1 0 0 1 1 0 BACK Full Bridge 1 1 0 1 1 0 1 0 0 1 FORWARD Full Bridge 1 1 1 0 1 0 1 0 0 1 FORWARD Full Bridge 1 1 1 1 1 0 0 1 1 0 BACK Full Bridge 1 1 0 1 1 pwm1 pwm1 pwm2 pwm2 PWM1 ->left PWM2->right Two Half Bridges 1 1 1 1 1 pwm1 pwm1 pwm2 pwm2 PWM1 ->left PWM2->right Two Half Bridges Table 14. Functional Description Table (continued) Drive EN PWM_EN DIR PWM1 IN1 IN2 UL DL UR DR Operation Configuration |
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