RM0352 datasheet(63/138 Pages) STMICROELECTRONICS

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RM0352

ARM© dual timer module (SP804)

137

Figure 13 shows the bit assignments for the registers.

Figure 13. Peripheral identification register bit assignment

Note:

When you design a system memory map you must remember that the peripheral has

a 4KB-memory footprint. The 4-bit revision number is implemented by instantiating

a component called RevAnd four times with its inputs tied off as appropriate, and the output

sent to the read multiplexor. All memory accesses to the peripheral identification registers

must be 32-bit, using the LDR instructions.

The four, 8-bit peripheral identification registers are described in the following subsections:

•

Timer peripheral ID0 register, TimerPeriphID0

•

Timer peripheral ID1 register, TimerPeriphID1

•

Timer peripheral ID2 register, TimerPeriphID2

•

Timer peripheral ID3 register, TimerPeriphID3

Timer peripheral ID0 register, TimerPeriphID0

The TimerPeriphID0 register is hard-coded and the fields in the register determine the reset

value.

Table 57 lists the bit assignments of the register.

Table 57. Timer peripheral ID0 register bit assignments

Bit

Name

Description

[31:8]

RESERVED, read undefined must be written as zeros

[7:0]

PartNumber0

These bits read back as 0x04

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