TX58TEGXDDKTAX0 datasheet(64/121 Pages) TOSHIBA

64 / 121 page

TOSHIBA CONFIDENTIAL

Tx58TEGxDDKTAx0

TENTATIVE 2013-07-10C

TC58TEG6DDKTA00 / TC58TEG6DDKTAI0

TH58TEG7DDKTA20 / TH58TEG7DDKTAK0

TH58TEG8DDKTA20 / TH58TEG8DDKTAK0

5.2.6. Cache Program Operation

The Cache Program function allows the host to write the next data for another page to the page register while a

page of data to be programmed to the Flash array for the selected LUN. When command 15h is issued, R/ B

returns high (i.e. ready) when a cache register is ready to be written after data in the cache register is transferred

to a page register. However, when command 10h is issued for the final page, R/ B turns to high after outstanding

program operation performed by previous Cache Program command and the program operation for the final page is

completed. SR[0] is valid for this command after SR[5] transitions from zero to one until the next transition. SR[1]

is valid for this command after SR[6] transitions from zero to one, and it is invalid after the first Cache Program

Command completion since there is no previous Cache Program operation. Cache Program operation shall work

only within a block. Figure 47 defines the Cache Program behavior and timings. Note that tPROG at the end of the

caching operation may be longer than typical as this time also includes completing the programming operation for

the previous page. Writing beyond the end of the page register is undefined.

Figure 47. Cache Program Timing

5.2.7. Block Erase Operation

The Block Erase operation is done on a block basis. Only three cycles of row addresses are required for Block Erase

operation and a page address within the cycles is ignored while plane and block address are valid. After Block

Erase operation passes, all bits in the block shall be set to one. SR[0] is valid for this command after SR[6]

transitions from zero to one(i.e. the selected LUN is ready) until the LUN goes in busy state by a next command.

Figure 48defines the Block Erase behavior and timings.

Figure 48. Block Erase Timing

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