TX58TEGXDDKTAX0 datasheet(77/121 Pages) TOSHIBA

77 / 121 page

TOSHIBA CONFIDENTIAL

Tx58TEGxDDKTAx0

TENTATIVE 2013-07-10C

TC58TEG6DDKTA00 / TC58TEG6DDKTAI0

TH58TEG7DDKTA20 / TH58TEG7DDKTAK0

TH58TEG8DDKTA20 / TH58TEG8DDKTAK0

5.3.4. Multi Page Sequential Cache Read Operation

Multi Page Sequential Cache Read operation provides fast sequential read function after the initial Multi Page

Read operation is set. With the primary command, once Multi Page Read operation performs, next page data can be

loaded to page register by command 31h without additional address setting while a host reads data, which is loaded

by Multi Page Read operation, from cache registers. Since the next page data are loaded to page registers during

host read-out period, R/ B turns to high (i.e. ready) in a short time after command 31h although data loading by

command 31h is being performed internally. If the previous data is still being loaded after command 31h, R/ B

busy state may take as long as tR, hence the maximum time of tDCBSYR is identical to tR. At the last page, command

3Fh shall be issued to transfer data from page registers to cache registers. Multi Page Sequential Cache Read

operation shall work only within a block of each plane and shall not be continued over the boundary of plane. Note

that the multi page addresses shall be set through 1st Set and 2nd Set of command with the Address Input

Restrictions for Multi Page Operation specified in section 5.3.2. Figure 64 and Figure 65 defines Multi Page

Sequential Cache Read behavior and timings. In the case of secondary command, make sure WP is held to High

level when Multi Page Sequential Cache Read operation is performed.

Figure 64. Example Timing with Multi Page Cache Read (Primary)

TX58TEGXDDKTAX0 データシート(PDF) 77 Page - Toshiba Semiconductor