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TX58TEGXDDKTAX0 データシート(PDF) 11 Page - Toshiba Semiconductor

部品番号 TX58TEGXDDKTAX0
部品情報  Semiconductor & Storage Products
PDF  121 Pages
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メーカー  TOSHIBA [Toshiba Semiconductor]
ホームページ  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TX58TEGXDDKTAX0 データシート(HTML) 11 Page - Toshiba Semiconductor

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TOSHIBA CONFIDENTIAL
Tx58TEGxDDKTAx0
TENTATIVE 2013-07-10C
10
TC58TEG6DDKTA00 / TC58TEG6DDKTAI0
TH58TEG7DDKTA20 / TH58TEG7DDKTAK0
TH58TEG8DDKTA20 / TH58TEG8DDKTAK0
•
Access time
Cell array to register TBD µs max
TBD µs typ.
Data Transfer rate
100 MHz
•
Program/Erase time
Auto Page Program
TBD µs/page typ.
Auto Block Erase
TBD ms/block typ.
•
Operating current
Read
TBD mA max. (per 1 chip)
Program (avg.)
TBD mA max. (per 1 chip)
Erase (avg.)
TBD mA max. (per 1 chip)
•
Reliability
Refer to APPLICATION NOTES AND COMMENTS.
1.4. Diagram Legend
Diagrams in the Toggle DDR1.0 datasheet use the following legend:
Command
This legend shows the command data. Refer to the Table 31 for more information about the command data.
Address
C1
C2
R1
R2
R3
This legend shows the Address data. The addresses are comprised of 2 cycles column address and 3 cycles row
address.
C1: Column address 1
C2: Column address 2
R1: Row address 1
R2: Row address 2
R3: Row address 3
W-Data
This legend shows Host writing data (data input) to the device.
R-Data
This legend shows Host reading data (data output) from the device.
SR[x]
This legend shows Host reading the status register within a particular LUN.



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