TX58TEGXDDKTAX0 datasheet(91/121 Pages) TOSHIBA

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TOSHIBA CONFIDENTIAL

Tx58TEGxDDKTAx0

TENTATIVE 2013-07-10C

TC58TEG6DDKTA00 / TC58TEG6DDKTAI0

TH58TEG7DDKTA20 / TH58TEG7DDKTAK0

TH58TEG8DDKTA20 / TH58TEG8DDKTAK0

Byte 0-3: Parameter page signature

This field contains the Parameter Page signature. When two or more bytes of the signature are valid, then it

denotes that a valid copy of the Paramter Page is present.

Byte 0 shall be set to 4Ah.

Byte 1 shall be set to 45h.

Byte 2 shall be set to 53h.

Byte 3 shall be set to 44h.

Byte 4-5: Revision number

This field indicates the revisions of the Paramter Page and standard that the target complies to. The target may

support multiple revisions of the standard. This is a bit field where each defined bit corresponds to a particular

specification revision that the target may support.

Bit 0 shall be cleared to zero.

Bit 1 when set to one indicates that the target supports vender specific Paramter Page.

Bit 2 when set to one indicates that the target supports Paramter Page revision 1.0 and standard revision 1.0.

Bits 3-15 are reserved and shall be cleared to zero.

Byte 6-7: Features supported

This field indicates the optional features that the target supports.

Bit 0 when set to one indicates that the target’s data bus width is 16-bits. Bit 0 when cleared to zero indicates that

the target’s data bus width is 8-bits. The host shall use the indicated data bus width for all commands that are

defined to be transferred at the bus width (x8 or x16). Note that some commands, like Read ID, always transfer

data as 8-bit only.

Bit 1 when set to one indicates that the target supports multiple LUN operations. If bit 1 is cleared to zero, then

the host shall not issue commands to a LUN unless all other LUNs on the target are idle (i.e. R/B_n is set to one).

Bit 2 when set to one indicates that the target supports non-sequential page programming operations, such that the

host may program pages within a block in arbitrary order. Bit 2 when cleared to zero indicates that the target does

not support non-sequential page programming operations. If bit 2 is cleared to zero, the host shall program all

pages within a block in order starting with page 0.

Bit 3 when set to one indicates that the target supports multi-plane program and erase operations.

Bit 4 when set to one indicates that the target supports multi-plane read operations.

Bit 5 when set to one indicates that the Synchronous DDR data interface is supported by the target. If bit 5 is set to

one, then the target shall indicate the Synchronous DDR timing modes supported in the Synchronous DDR timing

mode support field. Bit 5 when cleared to zero indicates that the Synchronous DDR data interface is not supported

by the target.

Bit 6 when set to one indicates that the Toggle Mode DDR data interface is supported by the target. If bit 6 is set to

one, then the target shall indicate the Toggle Mode DDR timing modes supported in the Toggle Mode DDR timing

mode support field. Bit 6 when cleared to zero indicates that the Toggle Mode DDR data interface is not supported

by the target.

Bit 7 when set to one indicates that the target supports external Vpp. If bit 7 is cleared to zero, then the target does

not support external Vpp.

Bit 8 when set to one indicates that the target supports clearing only the page register for the LUN addressed with

the Program (80h) command. If bit 8 is cleared to zero, then a Program (80h) command clears the page register for

each LUN that is part of the target. At power-on, the device clears the page register for each LUN that is part of the

target.

Bits 9-15 are reserved and shall be cleared to zero.

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