PIC16F15213 datasheet(67/439 Pages) MICROCHIP

67 / 439 page

Note:

In this specific case, ‘Release of POR’ and ‘Wake-up from Sleep’, there is no delay in start-up. The BOR

Ready flag (BORRDY = 1) will be set before the CPU is ready to execute instructions because the BOR circuit

is forced on by the BOREN bits.

Figure 10-2. Brown-Out Situations

TPWRT(1)

VBOR

VDD

Internal

Reset

VBOR

VDD

Internal

Reset

TPWRT(1)

< TPWRT

TPWRT(1)

VBOR

VDD

Internal

Reset

Rev. 30-000092A

4/12/2017

Note: TPWRT delay when the PWRTS bits are enabled (PWRTS != 00).

10.2.4

BOR Is Always Off

When the BOREN bits are programmed to ‘00’, the BOR is always disabled. In the configuration, setting the

SBOREN bit will have no affect on BOR operations.

10.3

MCLR Reset

The MCLR is an optional external input that can reset the device. The MCLR function is controlled by the MCLRE bit

and the LVP bit (see Table 10-2). The RMCLR bit will be set to ‘0’ if a MCLR has occurred.

Table 10-2. MCLR Configuration

MCLRE

LVP

MCLR

Enabled

Disabled

10.3.1

MCLR Enabled

When MCLR is enabled and the pin is held low, the device is held in Reset. The MCLR pin is connected to VDD

through an internal weak pull-up.

The device has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses.

Important: An internal Reset event (RESET instruction, BOR, WDT, POR, STKOVF, STKUNF) does not

drive the MCLR pin low.

PIC16F15213/14/23/24/43/44

Resets

and its subsidiaries

Data Sheet

DS40002195E-page 67

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