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PIC16F15213 データシート(PDF) 93 Page - Microchip Technology |
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PIC16F15213 データシート(HTML) 93 Page - Microchip Technology |
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93 / 439 page  12.9.2 PIE0 Name: PIE0 Offset: 0x716 Peripheral Interrupt Enable Register 0 Bit 7 6 5 4 3 2 1 0 TMR0IE IOCIE INTE Access R/W R/W R/W Reset 0 0 0 Bit 5 – TMR0IE Timer0 Interrupt Enable Value Description 1 TMR0 interrupts are enabled 0 TMR0 interrupts are disabled Bit 4 – IOCIE Interrupt-on-Change Enable Value Description 1 IOC interrupts are enabled 0 IOC interrupts are disabled Bit 0 – INTE External Interrupt Enable(1) Value Description 1 External interrupts are enabled 0 External interrupts are disabled Notes: 1. The external interrupt INT pin is selected by INTPPS. 2. Bit PEIE in the INTCON register must be set to enable any peripheral interrupt controlled by the PIE1 and PIE2 registers. Interrupt sources controlled by the PIE0 register do not require the PEIE bit to be set in order to allow interrupt vectoring (when the GIE bit in the INTCON register is set). PIC16F15213/14/23/24/43/44 Interrupts © 2020-2022 Microchip Technology Inc. and its subsidiaries Data Sheet DS40002195E-page 93 |
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