PIC16F15213 datasheet(68/439 Pages) MICROCHIP

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10.3.2

MCLR Disabled

When MCLR is disabled, the MCLR becomes input-only and pin functions such as internal weak pull-ups are under

software control.

10.4

Watchdog Timer (WDT) Reset

The Watchdog Timer generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out

period. The TO, PD and RWDT bits are changed to indicate a WDT Reset caused by the timer overflowing.

10.5

RESET Instruction

A RESET instruction will cause a device Reset. The RI bit will be set to ‘0’. See Table 10-4 for default conditions after

a RESET instruction has occurred.

10.6

Stack Overflow/Underflow Reset

The device can reset when the Stack Overflows or Underflows. The STKOVF or STKUNF bits indicate the Reset

condition. These Resets are enabled by setting the STVREN bit.

10.7

Power-Up Timer (PWRT)

The Power-up Timer provides up to a 64 ms time-out period on POR or BOR. The device is held in Reset as long as

PWRT is active. The PWRT delay allows additional time for the VDD to rise to an acceptable level.

The Power-up Timer is controlled by the PWRTS bits. The Power-up Timer starts after the release of the POR and

BOR. For additional information, refer to the “Power-up Trouble Shooting” Application Note AN607.

10.8

Start-Up Sequence

Upon the release of a POR or BOR, the following must occur before the device will begin executing:

Power-up Timer runs to completion (if enabled).

MCLR must be released (if enabled).

The Power-up Timer runs independently of MCLR Reset. If MCLR is kept low long enough, the Power-up Timer will

expire. Upon bringing MCLR high, the device will begin execution after 10 FOSC cycles (see Figure 10-3). This is

useful for testing purposes or for synchronizing more than one device operating in parallel.

PIC16F15213/14/23/24/43/44

Resets

and its subsidiaries

Data Sheet

DS40002195E-page 68

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