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PIC16F15213 データシート(PDF) 89 Page - Microchip Technology |
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PIC16F15213 データシート(HTML) 89 Page - Microchip Technology |
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89 / 439 page ![]() The following events happen when an interrupt event occurs while the GIE bit is set: • Current prefetched instruction is flushed • GIE bit is cleared • Current Program Counter (PC) is pushed onto the stack • Critical registers are automatically saved to the shadow registers (see Automatic Context Saving) • PC is loaded with the interrupt vector 0004h The firmware within the Interrupt Service Routine (ISR) may determine the source of the interrupt by polling the interrupt flag bits. The interrupt flag bits must be cleared before exiting the ISR to avoid repeated interrupts. Because the GIE bit is cleared, any interrupt that occurs while executing the ISR will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector. The RETFIE instruction exits the ISR by popping the previous address from the stack, restoring the saved context from the shadow registers and setting the GIE bit. For additional information on a specific interrupts operation, refer to its peripheral section. Important: 1. Individual interrupt flag bits are set, regardless of the state of any other enable bits. 2. All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again. 12.5 Interrupt Latency Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins. The interrupt is sampled during Q1 of the instruction cycle. The actual interrupt latency then depends on the instruction that is executing at the time the interrupt is detected. See the following figures for more details. Figure 12-2. Interrupt Latency Rev. 10-000269E 8/31/2016 Q1 Q1 Q1 Q1 Q1 Q1 Q1 Q2 Q2 Q2 Q2 Q2 Q2 Q2 Q3 Q3 Q3 Q3 Q3 Q3 Q3 Q4 Q4 Q4 Q4 Q4 Q4 Q4 CLKIN CLKOUT INT pin PC - 1 PC Fetch Execute PC - 2 PC - 1 PC PC + 1 NOP NOP PC = 0x0004 PC = 0x0004 PC = 0x0005 PC = 0x0005 PC = 0x0006 1 Cycle Instruction at PC Latency Valid Interrupt window(1) Indeterminate Latency(2) PIC16F15213/14/23/24/43/44 Interrupts © 2020-2022 Microchip Technology Inc. and its subsidiaries Data Sheet DS40002195E-page 89 |
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