PIC16F15213 datasheet(88/439 Pages) MICROCHIP

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12.

Interrupts

The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the

source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode.

Many peripherals can produce interrupts. Refer to the corresponding chapters for details.

A block diagram of the interrupt logic is shown in Figure 12-1.

Figure 12-1. Interrupt Logic

Filename:

Interrupt Logic.vsdx

Title:

Last Edit:

1/2/2020

First Used:

Notes:

Rev. Int errupt

1/2/2020

TMR0IF

TMR0IE

INTF

INTE

IOCIF

IOCIE

Interrupt

to CPU

Wake-up

(If in Sleep mode)

GIE

PIR0

PIRn

PEIE

PIE0

Peripheral Interrupts

PIEn

12.1

INTCON Register

The Interrupt Control (INTCON) register is readable and writable, and contains the Global Interrupt Enable (GIE),

Peripheral Interrupt Enable (PEIE), and External Interrupt Edge Select (INTEDG) bits.

12.2

PIE Registers

The Peripheral Interrupt Enable (PIE) registers contain the individual enable bits for the peripheral interrupts. Due to

the number of peripheral interrupt sources, there are three PIE registers in the PIC16F152 family.

12.3

PIR Registers

The Peripheral Interrupt Request (PIR) registers contain the individual flag bits for the peripheral interrupts. Due to

the number of peripheral interrupt sources, there are three PIR registers.

12.4

Operation

Interrupts are disabled upon any device Reset. They are enabled by setting the following bits:

• GIE bit

• PEIE bit (if the Interrupt Enable bit of the interrupt event is contained in the PIE registers)

• Interrupt Enable bit(s) for the specific interrupt event(s)

The PIR registers record individual interrupts via interrupt flag bits. Interrupt flag bits will be set, regardless of the

status of the GIE, PEIE and individual interrupt enable bits.

PIC16F15213/14/23/24/43/44

Interrupts

and its subsidiaries

Data Sheet

DS40002195E-page 88

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