PIC16F15213 datasheet(90/439 Pages) MICROCHIP

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Figure 12-3. INT Pin Interrupt Timing

Q3 Q4

CLKIN

INT pin

INTF

GIE

INSTRUCTION FLOW

Instruction

Fetched

Instruction

Executed

Interrupt Latency

PC + 1

0004h

0005h

Inst (0004h)

Inst (0005h)

For ced NOP

Inst (PC)

Inst (PC + 1)

Inst (PC – 1)

Inst (0004h)

For ced NOP

Inst (PC)

—

(1)

(2)

(4)

(5)

(1)

Rev. 30-000150A

6/27/2017

Notes:

INTF flag is sampled here (every Q1).

Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.

Latency is the same whether Inst (PC) is a single-cycle or a two-cycle instruction.

For minimum width of INT pulse, refer to AC specifications in the “Electrical Specifications” section.

INTF may be set any time during the Q4-Q1 cycles.

12.6

Interrupts During Sleep

Interrupts can be used to wake up from Sleep. To wake up from Sleep, the peripheral must be able to operate without

the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep.

On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the

processor will continue executing instructions after the SLEEP instruction. The instruction directly after the SLEEP

instruction will always be executed before branching to the ISR.

12.7

INT Pin

The INT pin can be used to generate an asynchronous edge-triggered interrupt. This interrupt is enabled by setting

the External Interrupt Enable (INTE) bit. The External Interrupt Edge Select (INTEDG) bit determines on which edge

the interrupt will occur. When the INTEDG bit is set, the rising edge will cause the interrupt. When the INTEDG bit

is clear, the falling edge will cause the interrupt. The External Interrupt Flag (INTF) bit will be set when a valid edge

appears on the INT pin. If the GIE and INTE bits are also set, the processor will redirect program execution to the

interrupt vector.

12.8

Automatic Context Saving

Upon entering an interrupt, the return PC address is saved on the stack. Additionally, the following registers are

automatically saved in the shadow registers:

• WREG register

• STATUS register (except for TO and PD)

• BSR register

PIC16F15213/14/23/24/43/44

Interrupts

and its subsidiaries

Data Sheet

DS40002195E-page 90

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