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PIC16F15213 データシート(PDF) 96 Page - Microchip Technology |
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PIC16F15213 データシート(HTML) 96 Page - Microchip Technology |
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96 / 439 page ![]() 12.9.5 PIR0 Name: PIR0 Offset: 0x70C Peripheral Interrupt Request Register 0 Bit 7 6 5 4 3 2 1 0 TMR0IF IOCIF INTF Access R/W/HS R R/W/HS Reset 0 0 0 Bit 5 – TMR0IF Timer0 Interrupt Flag Value Description 1 TMR0 register has overflowed (must be cleared by software) 0 TMR0 register has not overflowed Bit 4 – IOCIF Interrupt-on-Change Flag(2) Value Description 1 One or more of the IOCAF-IOCCF register bits are currently set, indicating an enabled edge was detected by the IOC module. 0 None of the IOCAF-IOCCF register bits are currently set Bit 0 – INTF External Interrupt Flag(1) Value Description 1 External interrupt has occurred 0 External interrupt has not occurred Notes: 1. The external interrupt INT pin is selected by INTPPS. 2. The IOCIF bit is the logical OR of all the IOCAF-IOCCF flags. Therefore, to clear the IOCIF flag, application firmware must clear all of the lower level IOCAF-IOCCF register bits. 3. Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable (GIE) bit. User software needs to ensure the appropriate interrupt flag bits are cleared before enabling an interrupt. PIC16F15213/14/23/24/43/44 Interrupts © 2020-2022 Microchip Technology Inc. and its subsidiaries Data Sheet DS40002195E-page 96 |
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