MPC5121E datasheet(28/86 Pages) FREESCALE

28 / 86 page

MPC5121E/MPC5123 Data Sheet, Rev. 1

Electrical and Thermal Characteristics

Freescale Semiconductor

NOTES:

1. The SYS_XTAL_IN frequency, Sys PLL, and CORE PLL settings must be chosen so that the resulting e300 clk, csb_clk, MCK,

frequencies do not exceed their respective maximum or minimum operating frequencies.

2. The values are valid for the user-operation mode. There can be deviations for test modes.

3. The selection of the peripheral clock frequencies needs to take care about requirements for baud rates and minimum frequency

limitation.

4.The DDR data rate is 2x the DDR memory bus frequency.

See the MPC5121e Reference Manual for more information on the clock subsystem.

3.3.3

Resets

The MPC5121e/MPC5123 has three reset pins:

•

PORESET - Power on Reset

•HRESET - Hard Reset

•SRESET - Software Reset

These signals are asynchronous I/O signals and can be asserted at any time. The input side uses a Schmitt trigger and requires

the same input characteristics as other MPC5121e/MPC5123 inputs, as specified in the DC Electrical Specifications section.

As long as VDD is not stable the HRESET output is not stable.

The timing relationship can be seen below.

NFC Clock

2.08

MHz

A1.7

DIU Clock

0.78

100

MHz

A1.8

SDHC Clock

0.78

66.6

MHz

A1.9

MBX Clock

6.25

100

MHz

A1.10

Table 17. Reset Rise / Fall Timing

Description

Min

Max

Unit

SpecID

PORESET1 fall time

1 Make sure that the PORESET does not carry any glitches. The

MPC5121e/MPC5123 has no filter to prevent them from getting into the chip.

—1

A3.4

PORESET rise time

—

A3.5

HRESET2,3 fall time

2 HRESET and SRESET must have a monotonous rise time.

3 The assertion of HRESET becomes active at Power on Reset without any

SYS_XTAL clock.

—1

A3.6

HRESET rise time

—

A3.7

SRESET fall time

—

A3.8

SRESET rise time

—

A3.9

Table 16. Clock Frequencies (continued)

Min

Max

Units

SpecID

Preliminary

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