MPC5121E datasheet(76/86 Pages) FREESCALE

76 / 86 page

MPC5121E/MPC5123 Data Sheet, Rev. 1

System Design Information

Freescale Semiconductor

The filter for System/Core PLLVDD to VSS should be connected to the power and ground planes, respectively, not fingers of

the planes.

In addition to keeping the filter components for System/Core PLLVDD as close as practical to the body of the MPC5121e as

previously mentioned, special care should be taken to avoid coupling switching power supply noise or digital switching noise

onto the portion of that supply between the filter and the MPC5121e.

The capacitors for C2 in the figure below should be rated X5R or better due to temperature performance.

Figure 57. Power Supply Filtering

4.3

Connection Recommendations

To ensure reliable operation, connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to

VDD_IO. Unused active high inputs should be connected to VSS. All NC (no-connect) signals must remain unconnected.

Power and ground connections must be made to all external VDD and VSS pins of the MPC5121e/MPC5123.

The unused AVDD_FUSEWR power should be connecetd to VSS directly or via a resistor.

For DDR or LPDDR modes the unused pins VTT[3:0] for DDR2 Termination voltage can be unconnected.

The SATA PHY needs to be powered even if it is not used in an application. In this case, you should not enable the SATA

oscillator and the SATA PHY by software.

Figure 58. Recommended Connection for Pins of Unused SATA PHY

AVDD device pin

Power supply

source

R1=10

C1=1

μF

C2=0.1

μF

SATA_XTALO

SATA_XTALI

VSS

SATA_RESREF

SATA_ANAVIZ

SATA_TXN

SATA_TXP

SATA_RXN

SATA_RXP

SATA_VDDA_1P2

SATA_VDDA_3P3

VDD_CORE

SATA_PLL_VDDA1P2

SATA_VDDA_VREG

1.7-2.6V

SATA_RX_VSSA

SATA_PLL_VSSA

VSS

SATA_TX_VSSA

VSS

VDD_CORE

VDD_IO

MPC5121e/MPC5123

Preliminary

MPC5121E データシート(PDF) 76 Page - Freescale Semiconductor, Inc

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