MPC5121E datasheet(70/86 Pages) FREESCALE

70 / 86 page

MPC5121E/MPC5123 Data Sheet, Rev. 1

Electrical and Thermal Characteristics

Freescale Semiconductor

Figure 49. Timing Diagram – SPI Slave Mode, Format 0 (CPHA = 0)

NOTE

Output timing is specified at a nominal 50 pF load.

Table 46. Timing Specifications – SPI Master Mode, Format 1 (CPHA = 1)

Sym

Description

Min

Max

Units

SpecID

SCK cycle time, programable in the PSC CCS register

30.0

—

A20.46

SCK pulse width, 50% SCK duty cycle

15.0

—

A20.47

Slave select clock delay, programable in the PSC CCS register

30.0

—

A20.48

Output data valid

—

8.9

A20.49

Input Data setup time

6.0

—

A20.50

Input Data hold time

1.0

—

A20.51

Slave disable lag time

—

TSCK

A20.52

Sequential Transfer delay, programable in the PSC CTUR / CTLR

15.0

—

A20.53

Clock falling time

—

7.9

A20.54

Clock rising time

—

7.9

A20.55

SCK

(CLKPOL=0)

SCK

(CLKPOL=1)

MOSI

Input

MISO

Output

Preliminary

MPC5121E データシート(PDF) 70 Page - Freescale Semiconductor, Inc

MPC5121E データシート(HTML) 70 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86

データシートダウンロード