MPC5121E datasheet(69/86 Pages) FREESCALE

部品番号	MPC5121E

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Electrical and Thermal Characteristics

MPC5121E/MPC5123 Data Sheet, Rev. 1

Freescale Semiconductor

Figure 48. Timing Diagram – SPI Master Mode, Format 0 (CPHA = 0)

NOTE

Output timing is specified at a nominal 50 pF load.

Table 45. Timing Specifications – SPI Slave Mode, Format 0 (CPHA = 0)

Sym

Description

Min

Max

Units

SpecID

SCK cycle time, programable in the PSC CCS register

30.0

—

A20.37

SCK pulse width, 50% SCK duty cycle

15.0

—

A20.38

Slave select clock delay

1.0

—

A20.39

Input Data setup time

1.0

—

A20.40

Input Data hold time

1.0

—

A20.41

Output data valid after SS

—

14.0

A20.42

Output data valid after SCK

—

14.0

A20.43

Slave disable lag time

0.0

—

A20.44

Minimum Sequential Transfer delay = 2 * IP Bus clock cycle time

30.0

—

A20.45

SCK

(CLKPOL=0)

SCK

(CLKPOL=1)

MOSI

Output

MISO

Input

Preliminary

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