| データシートサーチシステム |
|
MPC5121E データシート(PDF) 79 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
MPC5121E データシート(HTML) 79 Page - Freescale Semiconductor, Inc |
|
79 / 86 page ![]() System Design Information MPC5121E/MPC5123 Data Sheet, Rev. 1 Freescale Semiconductor 79 For a board with a COP (common on-chip processor) connector that accesses the JTAG interface and needs to reset the JTAG module, only wiring TRST and PORESET is not recommended. To reset the MPC5121e/MPC5123 via the COP connector, the HRESET pin of the COP should be connected to the HRESET pin of the MPC5121e/MPC5123. The circuitry shown in Figure 61 allows the COP to assert HRESET or TRST separately, while any other board sources can drive PORESET. 2See Note4 qack4 —— O 1TDO tdo — — I 1 With respect to the emulator tool’s perspective: Input is really an output from the embedded e300 core. Output is really an input to the core. 2 From the board under test, power sense for chip power. 3 HALTED is not available from e300 core. 4 Input to the e300 core to enable/disable soft-stop condition during breakpoints. MPC5121e/MPC5123 internally ties CORE_QACK to GND in its normal/functional mode (always asserted). Table 52. COP/BDM Interface Signals (continued) BDM Pin # MPC5121e/MPC51 23 I/O Pin BDM Connector Internal Pull Up/Down External Pull Up/Down I/O1 Preliminary |
|
リンク URL |
| ALLDATASHEETはお客様のビジネスに役立ちますか? [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | データシートへのリンク | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |