MPC5121E datasheet(77/86 Pages) FREESCALE

77 / 86 page

System Design Information

MPC5121E/MPC5123 Data Sheet, Rev. 1

Freescale Semiconductor

Figure 59. Recommended connection for pins of unused USB PHY

4.4

Pull-Up/Pull-Down Resistor Requirements

The MPC5121e/MPC5123 requires external pull-up or pull-down resistors on certain pins.

4.4.1

Pull-Down Resistor Requirements for TEST pin

The MPC5121e/MPC5123 requires a pull-down resistor on the test pin TEST.

4.4.2

Pull-Up Requirements for the PCI Control Lines

PCI control signals always require pull-up resistors on the motherboard (not the expansion board) to ensure that they contain

stable values when no agent is actively driving the bus. This includes PCI_FRAME, PCI_TRDY, PCI_IRDY, PCI_DEVSEL,

PCI_STOP, PCI_SERR, PCI_PERR, and PCI_REQ.

Refer to the PCI Local Bus specification.

4.5

JTAG

The MPC5121e/MPC5123 provides you with an IEEE 1149.1 JTAG interface to facilitate board/system testing. It also provides

a Common On-Chip Processor (COP) Interface, which shares the IEEE 1149.1 JTAG port.

The COP Interface provides access to the MPC5121e/MPC5123's embedded e300 processor and to other on-chip resources.

This interface provides a means for executing test routines and for performing software development and debug functions.

4.5.1

TRST

Boundary scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE 1149.1

specification but is provided on all processors that implement the PowerPC architecture. To obtain a reliable power-on reset

performance, the TRST signal must be asserted during power-on reset.

USB_XTALO

USB_XTALI

VSS

USB_TPA

USB_DN

USB_DP

Weak pull-up or pull-down

USB_UID

USB_VBUS

VSS

USB_PLL_PWR3

USB_PLL_GND

VSS

USB_VSSA_BIAS

USB_RREF

VSS

USB_VDDA_BIAS

VSS

VDD_IO

USB_VSSA

VSS

USB_VDDA

VDD_IO

MPC5121e/MPC5123

Preliminary

MPC5121E データシート(PDF) 77 Page - Freescale Semiconductor, Inc

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