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MPC5121E データシート(PDF) 75 Page - Freescale Semiconductor, Inc

部品番号 MPC5121E
部品情報  Advance Information
PDF  86 Pages
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メーカー  FREESCALE [Freescale Semiconductor, Inc]
ホームページ  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC5121E データシート(HTML) 75 Page - Freescale Semiconductor, Inc

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System Design Information
MPC5121E/MPC5123 Data Sheet, Rev. 1
Freescale Semiconductor
75
3.3.24
VIU
The Video Input Unit (VIU) is an interface which accepts the ITU656 format compatible video stream.
Figure 56 shows the VIU interface timing and Table 51 lists the timing parameters.
Figure 56. VIU Interface Timing Diagram
4
System Design Information
4.1
Power Up/Down Sequencing
Power sequencing between the 1.4 V power supply VDD_CORE and the remaing supplies is required to prevent excessive
current during power up phase.
The recommended power sequence is as follows:
Use 12V/millisecond or slower time for all supplies.
Power up VDD_IO, PLL_AVDD, VBAT_RTC (if not applied permanently), VDD_MEM_IO, AVDD_FUSERD, USB
PHY & SATA PHY supplies first in any order and then power up VDD_CORE. If required AVDD_FUSEWR should
be powered up afterwards.
All the supplies must reach the specified operating conditions before the PORESET can be released.
For power down, drop AVDD_FUSEWR to 0V first, drop VDD_CORE to 0V, and then drop all other supplies.
VDD_CORE should not exceed VDD_IO, VDD_MEM_IO, VBAT_RTC or PLL_AVDDs by more than 0.4 V at any
time, including power-up.
4.2
System and CPU Core AVDD Power Supply Filtering
Each of the independent PLL power supplies require filtering external to the device. The following drawing Figure 57 is a
recommendation for the required filter circuit.
Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize noise coupled from
nearby circuits.
All traces should be as low impedance as possible, especially ground pins to the ground plane.
Table 51. VIU Interface Timing Parameters
Parameter
Description
Min
Typ
Max
Unit
SpecID
fPIX_CK
VIU Pixel Clock Frequency
-
-
83
MHz
A24.1
tDSU
VIU Data Setup Time
2.5
-
-
ns
A24.2
tDHD
VIU Data Hold Time
2.5
-
-
ns
A24.3
fPIX_CLK
tDHD
tDSU
VIU_PIX_CLK
VIU_DATA[9:0]
Preliminary



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