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MPC5121E データシート(PDF) 80 Page - Freescale Semiconductor, Inc |
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MPC5121E データシート(HTML) 80 Page - Freescale Semiconductor, Inc |
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80 / 86 page ![]() MPC5121E/MPC5123 Data Sheet, Rev. 1 System Design Information Freescale Semiconductor 80 Figure 61. COP Connector Diagram 4.5.2.2 Boards Without COP Connector If the JTAG interface is not used, TRST should be tied to PORESET, so that it is asserted when the system reset signal (PORESET) is asserted. This ensures that the JTAG scan chain is initialized during power on. Figure 62 shows the connection of the JTAG interface without COP connector. 1 3 5 7 9 11 13 15 2 4 6 8 10 12 K 16 14 HRESET SRESET VDD_IO VDD_IO TRST VDD_IO TMS VDD_IO TCK VDD_IO TDI CKSTP_OUT TDO 3 11 16 4 9 12 7 62 15 1 10 5(3) 2(4) 13 NC NC NC TDO HRESET SRESET TRST TMS TCK TDI CKSTP_OUT VDD_IO 10Kohm 10Kohm 10Kohm 10Kohm 10Kohm COP Header COP Connector Physical Pinout halted qack VDD_IO 10Kohm PORESET PORESET VDD_IO 10Kohm CKSTP_IN (LPC_CLK) 8 CKSTP_IN VDD_IO 10Kohm Preliminary |
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