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ADC32RF83 データシート(PDF) 37 Page - Texas Instruments

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部品番号 ADC32RF83
部品情報  ADC32RF8x Dual-Channel, 3-GSPS Telecom Receiver and Feedback Devices
PDF  138 Pages
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メーカー  TI [Texas Instruments]
ホームページ  http://www.ti.com
Logo TI - Texas Instruments

ADC32RF83 データシート(HTML) 37 Page - Texas Instruments

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IQ 3 GSPS
N/2
ADC
NCO 2,
16 Bits
3 GSPS
IQ data, 3 GSPS
RX1 IQ Output
GPIO
SYSREF
RX2 IQ Output
NCO 1,
16 Bits
NCO 3,
16 Bits
NCO 4,
16 Bits
RX1 Real Output
Wideband IQ Output
2,3
Wideband Real Output
RX2 Real Output
JESD204B
fOUT / 4
2
fOUT / 4
fOUT / 4
LPF
LPF
2
LPF
LPF
N/2
2
LPF
LPF
IQ data
Real[ ]
Real[ ]
Real[ ]
IQ data
IQ data
37
ADC32RF80, ADC32RF83
www.ti.com
SBAS774A – MAY 2016 – REVISED DECEMBER 2016
Product Folder Links: ADC32RF80 ADC32RF83
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Additionally, the decimation filter block provides the option to convert the complex output back to real format at
twice the decimated, complex output rate. The filter response with a real output is identical to a complex output.
The band is centered in the middle of the Nyquist zone (mixed with fOUT / 4) based on a final output data rate of
fOUT.
8.3.4.1 Operating Mode: Receiver
In receiver mode, the DDC block can be configured to single- or dual-band operation, as shown in Figure 94.
Both DDC chains use the same decimation filter setting and the available options are discussed in the
Decimation Filters section. The decimation filter setting also directly affects the interface rate and number of
lanes of the JESD204B interface.
NOTE: Red traces show SYSREF going to the NCO blocks.
Figure 94. Decimation Filter Option for Single- or Dual-Band Operation



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