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ADC32RF83 データシート(PDF) 80 Page - Texas Instruments |
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ADC32RF83 データシート(HTML) 80 Page - Texas Instruments |
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80 / 138 page  80 ADC32RF80, ADC32RF83 SBAS774A – MAY 2016 – REVISED DECEMBER 2016 www.ti.com Product Folder Links: ADC32RF80 ADC32RF83 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated 8.5.3.3 Register 039h (address = 039h), Master Page Figure 154. Register 039h 7 6 5 4 3 2 1 0 0 ALWAYS WRITE 1 0 ALWAYS WRITE 1 0 0 PDN CHB EN SYNC TERM DIS W-0h W-0h W-0h W-0h W-0h R/W-0h R/W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 40. Register 039h Field Descriptions Bit Field Type Reset Description 7 0 W 0h Must write 0 6 ALWAYS WRITE 1 W 0h Always set this bit to 1 5 0 W 0h Must write 0 4 ALWAYS WRITE 1 W 0h Always set this bit to 1 3-2 0 W 0h Must write 0 1 PDN CHB EN R/W 0h This bit enables the power-down control of channel B through the SPI in register 20h. 0 = PDN control disabled 1 = PDN control enabled 0 SYNC TERM DIS R/W 0h This bit disables the on-chip, 100-Ω termination resistors on the SYNCB input. 0 = On-chip, 100-Ω termination enabled 1 = On-chip, 100-Ω termination disabled 8.5.3.4 Register 03Ch (address = 03Ch), Master Page Figure 155. Register 03Ch 7 6 5 4 3 2 1 0 0 SYSREF DEL EN 0 0 0 0 SYSREF DEL[4:3] W-0h R/W-0h W-0h W-0h W-0h W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 41. Register 03Ch Field Descriptions Bit Field Type Reset Description 7 0 W 0h Must write 0 6 SYSREF DEL EN R/W 0h This bit allows an internal delay to be added to the SYSREF input. 0 = SYSREF delay disabled 1 = SYSREF delay enabled through register settings [3Ch (bits 1-0), 5Ah (bits 7-5)] 5-2 0 W 0h Must write 0 1-0 SYSREF DEL[4:3] R/W 0h When the SYSREF delay feature is enabled (3Ch, bit 6) the delay can be adjusted in 25-ps steps; the first step is 175 ps. The PVT variation of each 25-ps step is ±10 ps. The 175-ps step is ±50 ps; see Table 43. |
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