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ADC32RF83 データシート(PDF) 71 Page - Texas Instruments

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部品番号 ADC32RF83
部品情報  ADC32RF8x Dual-Channel, 3-GSPS Telecom Receiver and Feedback Devices
PDF  138 Pages
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メーカー  TI [Texas Instruments]
ホームページ  http://www.ti.com
Logo TI - Texas Instruments

ADC32RF83 データシート(HTML) 71 Page - Texas Instruments

Back Button ADC32RF83 Datasheet HTML 67Page - Texas Instruments ADC32RF83 Datasheet HTML 68Page - Texas Instruments ADC32RF83 Datasheet HTML 69Page - Texas Instruments ADC32RF83 Datasheet HTML 70Page - Texas Instruments ADC32RF83 Datasheet HTML 71Page - Texas Instruments ADC32RF83 Datasheet HTML 72Page - Texas Instruments ADC32RF83 Datasheet HTML 73Page - Texas Instruments ADC32RF83 Datasheet HTML 74Page - Texas Instruments ADC32RF83 Datasheet HTML 75Page - Texas Instruments Next Button
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ADC32RF80, ADC32RF83
www.ti.com
SBAS774A – MAY 2016 – REVISED DECEMBER 2016
71
Product Folder Links: ADC32RF80 ADC32RF83
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Register Maps (continued)
Table 27. Register Map (continued)
REGISTER
ADDRESS
A[11:0] (Hex)
REGISTER DATA
7
6
5
4
3
2
1
0
Digital Gain Page Channel B (610105, M = 1)
0A6
0
0
0
0
DIGITAL GAIN
Main Digital Page Channel A (680000h, M = 1)
000
0
0
0
0
0
0
0
DIG CORE RESET
GBL
0A2
0
0
0
0
NQ ZONE EN
NYQUIST ZONE
Main Digital Page Channel B (680001h, M = 1)
000
0
0
0
0
0
0
0
0
0A2
0
0
0
0
NQ ZONE EN
NYQUIST ZONE
JESD DIGITAL PAGE (690000h, M = 1)
001
CTRL K
0
0
TESTMODE EN
0
LANE ALIGN
FRAME ALIGN
TX LINK DIS
002
SYNC REG
SYNC REG EN
0
0
12BIT MODE
JESD MODE0
003
LINK LAYER TESTMODE
LINK LAY RPAT
LMFC MASK
RESET
JESD MODE1
JESD MODE2
RAMP 12BIT
004
0
0
0
0
0
0
REL ILA SEQ
006
SCRAMBLE EN
0
0
0
0
0
0
0
007
0
0
0
FRAMES PER MULTIFRAME (K)
016
0
40X MODE
0
0
0
0
017
0
0
0
0
LANE0
POL
LANE1
POL
LANE2
POL
LANE3
POL
032
SEL EMP LANE 0
0
0
033
SEL EMP LANE 1
0
0
034
SEL EMP LANE 2
0
0
035
SEL EMP LANE 3
0
0
036
0
CMOS SYNCB
0
0
0
0
0
0
037
0
0
0
0
0
0
PLL MODE
03C
0
0
0
0
0
0
0
EN CMOS SYNCB
03E
0
MASK CLKDIV
SYSREF
MASK NCO
SYSREF
0
0
0
0
0



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