ADC32RF83 datasheet(54/138 Pages) TI

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ADC32RF80, ADC32RF83

SBAS774A – MAY 2016 – REVISED DECEMBER 2016

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NOTE

The number of converters increases in dual-band DDC mode and with a complex output.

Table 12. Test Pattern Options (Register 37h and 38h in Decimation Filter Page)

BIT

NAME

DEFAULT

DESCRIPTION

Address 37h,

38h (bits 7-0)

TEST PATTERN DDC1 I-

DATA,

TEST PATTERN DDC1 Q-

DATA,

TEST PATTERN DDC2 I-

DATA,

TEST PATTERN DDC2 Q-

DATA,

0000

Test pattern outputs onI and Q stream of channel A and B when DDC

option is chosen.

0000 = Normal operation using ADC output data

0001 = Outputs all 0s

0010 = Outputs all 1s

0011 = Outputs toggle pattern: output data are an alternating sequence of

10101010101010 and 01010101010101

0100 = Output digital ramp: output data increment by one LSB every

clock cycle from code 0 to 65535

0110 = Single pattern: output data are a custom pattern 1 (75h and 76h)

0111 Double pattern: output data alternate between custom pattern 1 and

custom pattern 2

1000 = Deskew pattern: output data are AAAAh

1001 = SYNC pattern: output data are FFFFh

8.3.10.2 Transport Layer

The transport layer maps the ADC output data into 8-bit octets and constructs the JESD204B frames using the

LMFS parameters. Tail bits or 0's are added when needed. Alternatively, the JESD204B long transport layer test

pattern can be substituted instead of the ADC data with the JESD frame, as shown in Table 13.

Table 13. Transport Layer Test Mode EN (Register 01h)

BIT

NAME

DEFAULT

DESCRIPTION

TESTMODE EN

Generates long transport layer test pattern mode according

to section 5.1.6.3 of the JESD204B specification.

0 = Test mode disabled

1 = Test mode disabled

8.3.10.3 Link Layer

The link layer contains the scrambler and the 8b, 10b encoding of any data passed on from the transport layer.

Additionally, the link layer also handles the initial lane alignment sequence that can be manually restarted.

The link layer test patterns are intended for testing the quality of the link (jitter testing and so forth). The test

patterns do not pass through the 8b, 10b encoder and contain the options listed in Table 14.

Table 14. Link Layer Test Mode (Register 03h)

BIT

NAME

DEFAULT

DESCRIPTION

7-5

LINK LAYER TESTMODE

000

Generates a pattern according to section 5.3.3.8.2 of the

JESD204B document.

000 = Normal ADC data

001 = D21.5 (high-frequency jitter pattern)

010 = K28.5 (mixed-frequency jitter pattern)

011 = Repeat the initial lane alignment (generates a K28.5

character and repeats lane alignment sequences

continuously)

100 = 12-octet random pattern (RPAT) jitter pattern

Furthermore, a 215 pseudo-random binary sequence (PRBS) can be enabled by setting up a custom test pattern

(AAAAh) in the ADC section and running AAAAh through the 8b, 10b encoder with scrambling enabled.

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