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ADC32RF83 データシート(PDF) 84 Page - Texas Instruments

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部品番号 ADC32RF83
部品情報  ADC32RF8x Dual-Channel, 3-GSPS Telecom Receiver and Feedback Devices
PDF  138 Pages
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メーカー  TI [Texas Instruments]
ホームページ  http://www.ti.com
Logo TI - Texas Instruments

ADC32RF83 データシート(HTML) 84 Page - Texas Instruments

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ADC32RF80, ADC32RF83
SBAS774A – MAY 2016 – REVISED DECEMBER 2016
www.ti.com
Product Folder Links: ADC32RF80 ADC32RF83
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
8.5.5 Digital Function Page (610000h, M = 1 for Channel A and 610100h, M = 1 for Channel B)
8.5.5.1 Register A6h (address = 0A6h), Digital Function Page
Figure 162. Register 0A6h
7
6
5
4
3
2
1
0
0
0
0
0
DIG GAIN
W-0h
W-0h
W-0h
W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 49. Register 0A6h Field Descriptions
Bit
Field
Type
Reset
Description
7-4
0
W
0h
Must write 0
3-0
DIG GAIN
R/W
0h
These bits set the digital gain of the ADC output data prior to
decimation up to 11 dB; see Table 50.
Table 50. DIG GAIN Bit Settings
SETTING
DIGITAL GAIN
0000
0 dB
0001
1 dB
0010
2 dB
…
…
1010
10 dB
1011
11 dB
8.5.6 Offset Corr Page Channel A (610000h, M = 1)
8.5.6.1 Register 034h (address = 034h), Offset Corr Page Channel A
Figure 163. Register 034h
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
SEL EXT EST
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 51. Register 034h Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
W
0h
Must write 0
0
SEL EXT EST
R/W
0h
This bit selects the external estimate for the offset correction
block; see the Using DC Coupling in the ADC32RF8x section.



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