データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

Preview PDF HTML

ADC32RF83 データシート(PDF) 90 Page - Texas Instruments

Click here to check the latest version.
部品番号 ADC32RF83
部品情報  ADC32RF8x Dual-Channel, 3-GSPS Telecom Receiver and Feedback Devices
PDF  138 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  TI [Texas Instruments]
ホームページ  http://www.ti.com
Logo TI - Texas Instruments

ADC32RF83 データシート(HTML) 90 Page - Texas Instruments

Back Button ADC32RF83 Datasheet HTML 86Page - Texas Instruments ADC32RF83 Datasheet HTML 87Page - Texas Instruments ADC32RF83 Datasheet HTML 88Page - Texas Instruments ADC32RF83 Datasheet HTML 89Page - Texas Instruments ADC32RF83 Datasheet HTML 90Page - Texas Instruments ADC32RF83 Datasheet HTML 91Page - Texas Instruments ADC32RF83 Datasheet HTML 92Page - Texas Instruments ADC32RF83 Datasheet HTML 93Page - Texas Instruments ADC32RF83 Datasheet HTML 94Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 90 / 138 page
background image
90
ADC32RF80, ADC32RF83
SBAS774A – MAY 2016 – REVISED DECEMBER 2016
www.ti.com
Product Folder Links: ADC32RF80 ADC32RF83
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
8.5.11 JESD Digital Page (6900h, M = 1)
8.5.11.1 Register 001h (address = 001h), JESD Digital Page
Figure 171. Register 001h
7
6
5
4
3
2
1
0
CTRL K
0
0
TESTMODE EN
0
LANE ALIGN
FRAME ALIGN
TX LINK DIS
R/W-0h
W-0h
W-0h
R/W-0h
W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 59. Register 001h Field Descriptions
Bit
Field
Type
Reset
Description
7
CTRL K
R/W
0h
This bit is the enable bit for the number of frames per
multiframe.
0 = Default is five frames per multiframe
1 = Frames per multiframe can be set in register 06h
6-5
0
R/W
0h
Must write 0
4
TESTMODE EN
0
This bit generates a long transport layer test pattern mode
according to section 5.1.6.3 of the JESD204B specification.
0 = Test mode disabled
1 = Test mode enabled
3
0
W
0h
Must write 0
2
LANE ALIGN
R/W
0h
This bit inserts a lane alignment character (K28.3) for the
receiver to align to the lane boundary per section 5.3.3.5 of the
JESD204B specification.
0 = Normal operation
1 = Inserts lane alignment characters
1
FRAME ALIGN
R/W
0h
This bit inserts a frame alignment character (K28.7) for the
receiver to align to the frame boundary per section 5.3.35 of the
JESD204B specification.
0 = Normal operation
1 = Inserts frame alignment characters
0
TX LINK DIS
R/W
0h
This bit disables sending the initial link alignment (ILA) sequence
when SYNC is deasserted.
0 = Normal operation
1 = ILA disabled



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


データシート ダウンロード

Go To PDF Page


リンク URL



ALLDATASHEETはお客様のビジネスに役立ちますか？  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   データシートへのリンク    |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com