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ADC32RF83 データシート(PDF) 98 Page - Texas Instruments

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部品番号 ADC32RF83
部品情報  ADC32RF8x Dual-Channel, 3-GSPS Telecom Receiver and Feedback Devices
PDF  138 Pages
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メーカー  TI [Texas Instruments]
ホームページ  http://www.ti.com
Logo TI - Texas Instruments

ADC32RF83 データシート(HTML) 98 Page - Texas Instruments

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98
ADC32RF80, ADC32RF83
SBAS774A – MAY 2016 – REVISED DECEMBER 2016
www.ti.com
Product Folder Links: ADC32RF80 ADC32RF83
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
8.5.12.2 Register 001h (address = 001h), Decimation Filter Page
Figure 188. Register 001h
7
6
5
4
3
2
1
0
0
0
0
0
DECIM FACTOR
W-0h
W-0h
W-0h
W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 73. Register 001h Field Descriptions
Bit
Field
Type
Reset
Description
7-4
0
W
0h
Must write 0
3-0
DECIM FACTOR
R/W
0h
These bits configure the decimation filter setting.
0000 = Divide-by-4 complex
0001 = Divide-by-6 complex
0010 = Divide-by-8 complex
0011 = Divide-by-9 complex
0100 = Divide-by-10 complex
0101 = Divide-by-12 complex
0110 = Not used
0111 = Divide-by-16 complex
1000 = Divide-by-18 complex
1001 = Divide-by-20 complex
1010 = Divide-by-24 complex
1011 = Not used
1100 = Divide-by-32 complex
8.5.12.3 Register 002h (address = 2h), Decimation Filter Page
Figure 189. Register 002h
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
DUAL BAND EN
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 74. Register 002h Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
W
0h
Must write 0
0
DUAL BAND EN
R/W
0h
This bit enables the dual-band DDC filter for the corresponding
channel.
0 = Single-band DDC; available in both ADC32RF80 and
ADC32RF83
1 = Dual-band DDC; available in ADC32RF80 only



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