ADC32RF83 datasheet(56/138 Pages) TI

56 / 138 page

SYNCb

SYSREF

LMFC Clock

LMFC Boundary

xxx

Transmit Data

K28.5

ILA

DATA

Multi

Frame

Code Group

Synchronization

Initial Lane Alignment

Data Transmission

ADC32RF80, ADC32RF83

SBAS774A – MAY 2016 – REVISED DECEMBER 2016

www.ti.com

Product Folder Links: ADC32RF80 ADC32RF83

Submit Documentation Feedback

Device Functional Modes (continued)

8.4.2.1 JESD204B Initial Lane Alignment (ILA)

The receiving device starts the initial lane alignment process by deasserting the SYNCB signal. The SYNCB

signal can be issued using the SYNCB input pins or by setting the proper SPI bits. When a logic low is detected

on the SYNCB input, the ADC32RF8x starts transmitting comma (K28.5) characters to establish the code group

synchronization, as shown in Figure 134.

When synchronization completes, the receiving device reasserts the SYNCB signal and the ADC32RF8x starts

the initial lane alignment sequence with the next local multiframe clock boundary. The ADC32RF8x transmits four

multiframes, each containing K frames (K is SPI programmable). Each of the multiframes contains the frame start

and end symbols. The second multiframe also contains the JESD204 link configuration data.

Figure 134. JESD Internal Timing Information

8.4.2.2 JESD204B Frame Assembly

The JESD204B standard defines the following parameters:

•

F is the number of octets per frame clock period

•

L is the number of lanes per link

•

M is the number of converters for the device

•

S is the number of samples per frame

ADC32RF83 データシート(PDF) 56 Page - Texas Instruments

ADC32RF83 データシート(HTML) 56 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

データシートダウンロード