データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

Preview PDF HTML

ADC32RF83 データシート(PDF) 103 Page - Texas Instruments

Click here to check the latest version.
部品番号 ADC32RF83
部品情報  ADC32RF8x Dual-Channel, 3-GSPS Telecom Receiver and Feedback Devices
PDF  138 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  TI [Texas Instruments]
ホームページ  http://www.ti.com
Logo TI - Texas Instruments

ADC32RF83 データシート(HTML) 103 Page - Texas Instruments

Back Button ADC32RF83 Datasheet HTML 99Page - Texas Instruments ADC32RF83 Datasheet HTML 100Page - Texas Instruments ADC32RF83 Datasheet HTML 101Page - Texas Instruments ADC32RF83 Datasheet HTML 102Page - Texas Instruments ADC32RF83 Datasheet HTML 103Page - Texas Instruments ADC32RF83 Datasheet HTML 104Page - Texas Instruments ADC32RF83 Datasheet HTML 105Page - Texas Instruments ADC32RF83 Datasheet HTML 106Page - Texas Instruments ADC32RF83 Datasheet HTML 107Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 103 / 138 page
background image
103
ADC32RF80, ADC32RF83
www.ti.com
SBAS774A – MAY 2016 – REVISED DECEMBER 2016
Product Folder Links: ADC32RF80 ADC32RF83
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
8.5.12.16 Register 011h (address = 011h), Decimation Filter Page
Figure 202. Register 011h
7
6
5
4
3
2
1
0
0
0
0
0
0
0
LMFC RESET MODE
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 87. Register 011h Field Descriptions
Bit
Field
Type
Reset
Description
7-2
0
W
0h
Must write 0
1-0
LMFC RESET MODE
R/W
0h
These bits reset the configuration for all DDCs and NCOs.
00 = All DDCs and NCOs are reset with every LMFC RESET
01 = Reset with first LMFC RESET after DDC start. Afterwards,
reset only when analog clock dividers are resynchronized.
10 = Reset with first LMFC RESET after DDC start. Afterwards,
whenever analog clock dividers are resynchronized, use two
LMFC resets.
11 = Do not use an LMFC reset at all. Reset the DDCs only
when a DDC start is asserted and afterwards continue normal
operation. Deterministic latency is not ensured.
8.5.12.17 Register 014h (address = 014h), Decimation Filter Page
Figure 203. Register 014h
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
DDC0 6DB GAIN
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 88. Register 014h Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
W
0h
Must write 0
0
DDC0 6DB GAIN
R/W
0h
This bit scales the output of DDC0 by 2 (6 dB) to compensate
for real-to-complex conversion and image suppression. This
scaling does not apply to the high-bandwidth filter path (divide-
by-4 and -6); see register 1Fh.
0 = Normal operation
1 = 6-dB digital gain is added



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


データシート ダウンロード

Go To PDF Page


リンク URL



ALLDATASHEETはお客様のビジネスに役立ちますか？  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   データシートへのリンク    |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com