ADC32RF83 datasheet(128/138 Pages) TI

128 / 138 page

AVDD

(1.15 V)

DVDD

(1.15 V)

AVDD19

(1.9 V)

128

ADC32RF80, ADC32RF83

SBAS774A – MAY 2016 – REVISED DECEMBER 2016

www.ti.com

Product Folder Links: ADC32RF80 ADC32RF83

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10 Power Supply Recommendations

The DVDD power supply (1.15 V) must be stable before ramping up the AVDD19 supply (1.9 V), as shown in

Figure 265. The AVDD supply (1.15 V) can come up in any order during the power sequence. The power

supplies can ramp up at any rate and there is no hard requirement for the time delay between DVDD (1.15 V)

ramping up to AVDD (1.9 V) ramping up (which can be in orders of microseconds but is recommended to be a

few milliseconds).

Figure 265. Power Sequencing for the ADC32RF8x Family of devices

11 Layout

11.1 Layout Guidelines

The device evaluation module (EVM) layout can be used as a reference layout to obtain the best performance. A

layout diagram of the EVM top layer is provided in Figure 266. The ADC32RF45/RF80 EVM Quick Startup Guide

provides a complete layout of the EVM. Some important points to remember during board layout are:

•

Analog inputs are located on opposite sides of the device pinout to ensure minimum crosstalk on the package

level. To minimize crosstalk onboard, the analog inputs must exit the pinout in opposite directions, as shown

in the reference layout of Figure 266 as much as possible.

•

In the device pinout, the sampling clock is located on a side perpendicular to the analog inputs in order to

minimize coupling. This configuration is also maintained on the reference layout of Figure 266 as much as

possible.

•

Keep digital outputs away from the analog inputs. When these digital outputs exit the pinout, the digital output

traces must not be kept parallel to the analog input traces because this configuration can result in coupling

from the digital outputs to the analog inputs and degrade performance. All digital output traces to the receiver

[such as field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs)] must be

matched in length to avoid skew among outputs.

•

At each power-supply pin (AVDD, DVDD, or AVDD19), keep a 0.1-µF decoupling capacitor close to the

device. A separate decoupling capacitor group consisting of a parallel combination of 10-µF, 1-µF, and 0.1-µF

capacitors can be kept close to the supply source.

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