H8SXSLASH1663M datasheet(35/1504 Pages) RENESAS

35 / 1504 page

Section 1 Overview

Rev. 2.00 Sep. 24, 2008 Page 3 of 1468

REJ09B0412-0200

Classification

Module/

Function

Description

CPU

MCU

operating

mode

Mode 1: User boot mode

(selected by driving the MD2 and MD1 pins low and

driving the MD0 pin high)

Mode 2: Boot mode

(selected by driving the MD2 and MD0 pins low and

driving the MD1 pin high)

Mode 3: Boundary scan enabled single chip mode

(selected by driving the MD2 pin low and driving the MD1

and MD0 pins high)

Mode 4: On-chip ROM disabled external extended mode, 16-bit

bus (selected by driving the MD1 and MD0 pins low and

driving the MD2 pin high)

Mode 5: On-chip ROM disabled external extended mode, 8-bit bus

(selected by driving the MD1 pin low and driving the MD2

and MD0 pins high)

Mode 6: On-chip ROM enabled external extended mode

(selected by driving the MD0 pin low and driving the MD2

and MD1 pins high)

Mode 7: Single-chip mode (can be externally extended)

(selected by driving the MD2, MD1, and MD0 pins high)

• Low power consumption state (transition driven by the SLEEP

instruction)

Power on reset (POR) *

• At power-on or low power supply voltage, an internal reset

signal is generated

Voltage detection circuit

(LVD)*

• At low power supply voltage, an internal reset and an interrupt

are generated.

Interrupt

controller

(INTC)

• 13 external interrupt pins (NMI, and IRQ11 to IRQ0)

• Internal interrupt sources

H8SX/1668R Group: 124 pins

H8SX/1668M Group: 125 pins

• Two interrupt control modes (specified by the interrupt control

• Eight priority orders specifiable (by setting the interrupt priority

• Independent vector addresses

Interrupt

(source)

Break

interrupt

(UBC)

• Break point can be set for four channels

• Address break can be set for CPU instruction fetch cycles

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