H8SXSLASH1663M datasheet(23/1504 Pages) RENESAS

23 / 1504 page

Rev. 2.00 Sep. 24, 2008 Page xxiii of xxxii

17.3.3

EXCKSN=0 Operation ..................................................................................... 850

17.4

Interrupt Source ................................................................................................................853

17.5

Usage Notes ...................................................................................................................... 854

17.5.1

Changing Values of Bits EXCKSN, CKS1, and CKS0 .................................... 854

17.5.2

Note on Register Initialization .......................................................................... 854

17.5.3

Usage Notes on 32K Timer............................................................................... 854

Section 18 Watchdog Timer (WDT)..................................................................855

18.1

Features............................................................................................................................. 855

18.2

Input/Output Pin ............................................................................................................... 856

18.3

Register Descriptions ........................................................................................................ 857

18.3.1

Timer Counter (TCNT)..................................................................................... 857

18.3.2

Timer Control/Status Register (TCSR)............................................................. 857

18.3.3

Reset Control/Status Register (RSTCSR)......................................................... 860

18.4

Operation .......................................................................................................................... 861

18.4.1

Watchdog Timer Mode ..................................................................................... 861

18.4.2

Interval Timer Mode ......................................................................................... 863

18.5

Interrupt Source ................................................................................................................863

18.6

Usage Notes ...................................................................................................................... 864

18.6.1

Notes on Register Access.................................................................................. 864

18.6.2

Conflict between Timer Counter (TCNT) Write and Increment....................... 865

18.6.3

Changing Values of Bits CKS2 to CKS0.......................................................... 865

18.6.4

Switching between Watchdog Timer Mode and Interval Timer Mode............. 865

18.6.5

Internal Reset in Watchdog Timer Mode.......................................................... 866

18.6.6

System Reset by

WDTOVF Signal................................................................... 866

18.6.7

Transition to Watchdog Timer Mode or Software Standby Mode.................... 866

Section 19 Serial Communication Interface (SCI, IrDA, CRC).......................867

19.1

Features............................................................................................................................. 867

19.2

Input/Output Pins.............................................................................................................. 872

19.3

Register Descriptions ........................................................................................................ 873

19.3.1

Receive Shift Register (RSR) ........................................................................... 875

19.3.2

Receive Data Register (RDR) ........................................................................... 875

19.3.3

Transmit Data Register (TDR).......................................................................... 876

19.3.4

Transmit Shift Register (TSR) .......................................................................... 876

19.3.5

Serial Mode Register (SMR) ............................................................................ 876

19.3.6

Serial Control Register (SCR)........................................................................... 880

19.3.7

Serial Status Register (SSR) ............................................................................. 885

19.3.8

Smart Card Mode Register (SCMR) ................................................................. 894

19.3.9

Bit Rate Register (BRR) ................................................................................... 895

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