H8SXSLASH1663M datasheet(56/1504 Pages) RENESAS

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Section 1 Overview

Rev. 2.00 Sep. 24, 2008 Page 24 of 1468

REJ09B0412-0200

Classification

Pin Name

I/O

Description

Address bus

A23 to A0

Output

Output pins for the address bits.

Data bus

D15 to D0

Input/

output

Input and output for the bidirectional data bus. These pins

also output addresses when accessing an address–data

multiplexed I/O interface space.

BREQ

Input

External bus-master modules assert this signal to request

the bus.

BREQO

Output

Internal bus-master modules assert this signal to request

access to the external space via the bus in the external bus

released state.

BACK

Output

Bus acknowledge signal, which indicates that the bus has

been released.

BS-A/BS-B

Output

Indicates the start of a bus cycle.

Output

Strobe signal which indicates that the output address on the

address bus is valid in access to the basic bus interface or

byte control SRAM interface space.

Output

This signal is used to hold the address when accessing the

address-data multiplexed I/O interface space.

Output

Strobe signal which indicates that reading from the basic bus

interface space is in progress.

RD/

WR-A/RD/WR-B Output

Indicates the direction (input or output) of the data bus.

LHWR

Output

Strobe signal which indicates that the higher-order byte (D15

to D8) is valid in access to the basic bus interface space.

LLWR

Output

Strobe signal which indicates that the lower-order byte (D7 to

D0) is valid in access to the basic bus interface space.

LUB

Output

Strobe signal which indicates that the higher-order byte (D15

to D8) is valid in access to the byte control SRAM interface

space.

Bus control

LLB

Output

Strobe signal which indicates that the lower-order byte (D7 to

D0) is valid in access to the byte control SRAM interface

space.

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