H8SXSLASH1663M datasheet(13/1504 Pages) RENESAS

13 / 1504 page

Rev. 2.00 Sep. 24, 2008 Page xiii of xxxii

Section 8 User Break Controller (UBC) ............................................................171

8.1

Features............................................................................................................................. 171

8.2

Block Diagram.................................................................................................................. 172

8.3

Register Descriptions ........................................................................................................ 173

8.3.1

Break Address Register n (BARA, BARB, BARC, BARD) ............................ 174

8.3.2

Break Address Mask Register n (BAMRA, BAMRB, BAMRC, BAMRD) .... 175

8.3.3

Break Control Register n (BRCRA, BRCRB, BRCRC, BRCRD) ................... 176

8.4

Operation .......................................................................................................................... 178

8.4.1

Setting of Break Control Conditions................................................................. 178

8.4.2

PC Break ........................................................................................................... 178

8.4.3

Condition Match Flag ....................................................................................... 179

8.5

Usage Notes ...................................................................................................................... 180

Section 9 Bus Controller (BSC).........................................................................183

9.1

Features............................................................................................................................. 183

9.2

Register Descriptions ........................................................................................................ 186

9.2.1

Bus Width Control Register (ABWCR)............................................................ 187

9.2.2

Access State Control Register (ASTCR) .......................................................... 188

9.2.3

Wait Control Registers A and B (WTCRA, WTCRB) ..................................... 189

9.2.4

Read Strobe Timing Control Register (RDNCR) ............................................. 194

9.2.5

CS Assertion Period Control Registers (CSACR) ............................................ 195

9.2.6

Idle Control Register (IDLCR) ......................................................................... 198

9.2.7

Bus Control Register 1 (BCR1) ........................................................................ 200

9.2.8

Bus Control Register 2 (BCR2) ........................................................................ 202

9.2.9

Endian Control Register (ENDIANCR)............................................................ 203

9.2.10

SRAM Mode Control Register (SRAMCR) ..................................................... 204

9.2.11

Burst ROM Interface Control Register (BROMCR)......................................... 205

9.2.12

Address/Data Multiplexed I/O Control Register (MPXCR) ............................. 207

9.2.13

DRAM Control Register (DRAMCR) .............................................................. 208

9.2.14

DRAM Access Control Register (DRACCR)................................................... 213

9.2.15

Synchronous DRAM Control Register (SDCR) ............................................... 214

9.2.16

Refresh Control Register (REFCR) .................................................................. 215

9.2.17

Refresh Timer Counter (RTCNT)..................................................................... 219

9.2.18

Refresh Time Constant Register (RTCOR) ...................................................... 219

9.3

Bus Configuration............................................................................................................. 220

9.4

Multi-Clock Function and Number of Access Cycles ...................................................... 221

9.5

External Bus...................................................................................................................... 225

9.5.1

Input/Output Pins .............................................................................................. 225

9.5.2

Area Division.................................................................................................... 229

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