H8SXSLASH1663M datasheet(24/1504 Pages) RENESAS

24 / 1504 page

Rev. 2.00 Sep. 24, 2008 Page xxiv of xxxii

19.3.10

Serial Extended Mode Register (SEMR_2) ...................................................... 902

19.3.11

Serial Extended Mode Register 5 and 6 (SEMR_5 and SEMR_6) ................... 904

19.3.12

IrDA Control Register (IrCR)........................................................................... 911

19.4

Operation in Asynchronous Mode .................................................................................... 912

19.4.1

Data Transfer Format........................................................................................ 913

19.4.2

Receive Data Sampling Timing and Reception Margin in Asynchronous

Mode................................................................................................................. 914

19.4.3

Clock................................................................................................................. 915

19.4.4

SCI Initialization (Asynchronous Mode) .......................................................... 916

19.4.5

Serial Data Transmission (Asynchronous Mode) ............................................. 917

19.4.6

Serial Data Reception (Asynchronous Mode) .................................................. 919

19.5

Multiprocessor Communication Function ........................................................................ 923

19.5.1

Multiprocessor Serial Data Transmission ......................................................... 925

19.5.2

Multiprocessor Serial Data Reception .............................................................. 926

19.6

Operation in Clocked Synchronous Mode (SCI_0, 1, 2, and 4 only)................................ 929

19.6.1

Clock................................................................................................................. 929

19.6.2

SCI Initialization (Clocked Synchronous Mode) (SCI_0, 1, 2, and 4 only) ..... 930

19.6.3

Serial Data Transmission (Clocked Synchronous Mode)

(SCI_0, 1, 2, and 4 only)................................................................................... 931

19.6.4

Serial Data Reception (Clocked Synchronous Mode)

(SCI_0, 1, 2, and 4 only)................................................................................... 933

19.6.5

Simultaneous Serial Data Transmission and Reception

(Clocked Synchronous Mode) (SCI_0, 1, 2, and 4 only).................................. 934

19.7

Operation in Smart Card Interface Mode.......................................................................... 936

19.7.1

Sample Connection ........................................................................................... 936

19.7.2

Data Format (Except in Block Transfer Mode) ................................................ 937

19.7.3

Block Transfer Mode ........................................................................................ 938

19.7.4

Receive Data Sampling Timing and Reception Margin ................................... 939

19.7.5

Initialization...................................................................................................... 940

19.7.6

Data Transmission (Except in Block Transfer Mode) ...................................... 941

19.7.7

Serial Data Reception (Except in Block Transfer Mode) ................................. 944

19.7.8

Clock Output Control (Only SCI_0, 1, 2, and 4) .............................................. 945

19.8

IrDA Operation ................................................................................................................. 947

19.9

Interrupt Sources...............................................................................................................950

19.9.1

Interrupts in Normal Serial Communication Interface Mode ........................... 950

19.9.2

Interrupts in Smart Card Interface Mode .......................................................... 951

19.10 Usage Notes ...................................................................................................................... 953

19.10.1

Module Stop Function Setting .......................................................................... 953

19.10.2

Break Detection and Processing ....................................................................... 953

19.10.3

Mark State and Break Detection ....................................................................... 953

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