H8SXSLASH1663M datasheet(99/1504 Pages) RENESAS

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Section 2 CPU

Rev. 2.00 Sep. 24, 2008 Page 67 of 1468

REJ09B0412-0200

2.8

Addressing Modes and Effective Address Calculation

The H8SX CPU supports the 11 addressing modes listed in table 2.12. Each instruction uses a

subset of these addressing modes.

Bit manipulation instructions use register direct, register indirect, or absolute addressing mode to

specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or

immediate (3-bit) addressing mode to specify a bit number in the operand.

Table 2.12

Addressing Modes

No. Addressing Mode

Symbol

@ERn

@(d:2,ERn)/@(d:16,ERn)/@(d:32,ERn)

Index register indirect with displacement

@(d:16, RnL.B)/@(d:16,Rn.W)/@(d:16,ERn.L)

@(d:32, RnL.B)/@(d:32,Rn.W)/@(d:32,ERn.L)

@ERn•

@•ERn

@ERn•

Absolute address

@aa:8/@aa:16/@aa:24/@aa:32

Immediate

#xx:3/#xx:4/#xx:8/#xx:16/#xx:32

Program-counter relative

@(d:8,PC)/@(d:16,PC)

Program-counter relative with index register

@(RnL.B,PC)/@(Rn.W,PC)/@(ERn.L,PC)

Memory indirect

@@aa:8

Extended memory indirect

@@vec:7

2.8.1

The operand value is the contents of an 8-, 16-, or 32-bit general register which is specified by the

R0H to R7H and R0L to R7L can be specified as 8-bit registers.

R0 to R7 and E0 to E7 can be specified as 16-bit registers.

ER0 to ER7 can be specified as 32-bit registers.

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