H8SXSLASH1663M datasheet(12/1504 Pages) RENESAS

12 / 1504 page

Rev. 2.00 Sep. 24, 2008 Page xii of xxxii

6.7

Instruction Exception Handling ........................................................................................ 124

6.7.1

Trap Instruction ................................................................................................ 124

6.7.2

Sleep Instruction Exception Handling .............................................................. 125

6.7.3

Exception Handling by Illegal Instruction ........................................................ 126

6.8

Stack Status after Exception Handling ............................................................................. 127

6.9

Usage Note ....................................................................................................................... 128

Section 7 Interrupt Controller............................................................................ 129

7.1

Features............................................................................................................................. 129

7.2

Input/Output Pins.............................................................................................................. 131

7.3

Register Descriptions........................................................................................................ 131

7.3.1

Interrupt Control Register (INTCR) ................................................................. 132

7.3.2

CPU Priority Control Register (CPUPCR) ....................................................... 133

7.3.3

Interrupt Priority Registers A to O, Q, and R (IPRA to IPRO, IPRQ, and

IPRR) ................................................................................................................ 135

7.3.4

IRQ Enable Register (IER) ............................................................................... 137

7.3.5

IRQ Sense Control Registers H and L (ISCRH, ISCRL).................................. 138

7.3.6

IRQ Status Register (ISR)................................................................................. 144

7.3.7

Software Standby Release IRQ Enable Register (SSIER) ................................ 145

7.4

Interrupt Sources...............................................................................................................147

7.4.1

External Interrupts ............................................................................................ 147

7.4.2

Internal Interrupts ............................................................................................. 148

7.5

Interrupt Exception Handling Vector Table...................................................................... 149

7.6

Interrupt Control Modes and Interrupt Operation............................................................. 156

7.6.1

Interrupt Control Mode 0 .................................................................................. 156

7.6.2

Interrupt Control Mode 2 .................................................................................. 158

7.6.3

Interrupt Exception Handling Sequence ........................................................... 160

7.6.4

Interrupt Response Times ................................................................................. 161

7.6.5

DTC and DMAC Activation by Interrupt ......................................................... 162

7.7

CPU Priority Control Function Over DTC, DMAC and EXDMAC ................................ 165

7.8

Usage Notes ...................................................................................................................... 168

7.8.1

Conflict between Interrupt Generation and Disabling ...................................... 168

7.8.2

Instructions that Disable Interrupts ................................................................... 169

7.8.3

Times when Interrupts are Disabled ................................................................. 169

7.8.4

Interrupts during Execution of EEPMOV Instruction ...................................... 169

7.8.5

Interrupts during Execution of MOVMD and MOVSD Instructions................ 169

7.8.6

Interrupts of Peripheral Modules ...................................................................... 170

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