H8SXSLASH1663M datasheet(37/1504 Pages) RENESAS

37 / 1504 page

Section 1 Overview

Rev. 2.00 Sep. 24, 2008 Page 5 of 1468

REJ09B0412-0200

Classification

Module/

Function

Description

Bus formats

• External memory interfaces (for the connection of ROM, burst

ROM, SRAM, byte control SRAM, DRAM, and synchronous

DRAM)

• Address/data bus format: Support for both separate and

multiplexed buses (8-bit access or 16-bit access)

External bus

extension

Bus

controller

(BSC)

• Endian conversion function for connecting devices in little-

endian format

Clock

Clock pulse

generator

(CPG)

• One clock generation circuit available

• Separate clock signals are provided for each of functional

modules (detailed below) and each is independently specifiable

(multi-clock function)

 System-intended data transfer modules, i.e. the CPU, runs

in synchronization with the system clock (I

φ): 8 to 50 MHz

 Internal peripheral functions run in synchronization with the

peripheral module clock (P

φ): 8 to 35 MHz

 Modules in the external space are supplied with the external

bus clock (B

φ): 8 to 50 MHz

• Includes a PLL frequency multiplication circuit and frequency

divider, so the operating frequency is selectable

• Five low-power-consumption modes: Sleep mode, all-module-

clock-stop mode, software standby mode, deep software

standby mode, and hardware standby mode

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