H8SXSLASH1663M datasheet(18/1504 Pages) RENESAS

18 / 1504 page

Rev. 2.00 Sep. 24, 2008 Page xviii of xxxii

Section 12 Data Transfer Controller (DTC) ...................................................... 559

12.1

Features............................................................................................................................. 559

12.2

Register Descriptions........................................................................................................ 561

12.2.1

DTC Mode Register A (MRA) ......................................................................... 562

12.2.2

DTC Mode Register B (MRB).......................................................................... 563

12.2.3

DTC Source Address Register (SAR)............................................................... 564

12.2.4

DTC Destination Address Register (DAR)....................................................... 565

12.2.5

DTC Transfer Count Register A (CRA) ........................................................... 565

12.2.6

DTC Transfer Count Register B (CRB)............................................................ 566

12.2.7

DTC enable registers A to F (DTCERA to DTCERF) ..................................... 566

12.2.8

DTC Control Register (DTCCR) ...................................................................... 567

12.2.9

DTC Vector Base Register (DTCVBR)............................................................ 569

12.3

Activation Sources............................................................................................................ 569

12.4

Location of Transfer Information and DTC Vector Table................................................ 569

12.5

Operation .......................................................................................................................... 574

12.5.1

Bus Cycle Division ........................................................................................... 576

12.5.2

Transfer Information Read Skip Function ........................................................ 578

12.5.3

Transfer Information Writeback Skip Function................................................ 579

12.5.4

Normal Transfer Mode ..................................................................................... 579

12.5.5

Repeat Transfer Mode ...................................................................................... 580

12.5.6

Block Transfer Mode ........................................................................................ 582

12.5.7

Chain Transfer .................................................................................................. 583

12.5.8

Operation Timing.............................................................................................. 584

12.5.9

Number of DTC Execution Cycles ................................................................... 586

12.5.10

DTC Bus Release Timing ................................................................................. 587

12.5.11

DTC Priority Level Control to the CPU ........................................................... 587

12.6

DTC Activation by Interrupt............................................................................................. 588

12.7

Examples of Use of the DTC ............................................................................................ 589

12.7.1

Normal Transfer Mode ..................................................................................... 589

12.7.2

Chain Transfer .................................................................................................. 589

12.7.3

Chain Transfer when Counter = 0..................................................................... 590

12.8

Interrupt Sources...............................................................................................................592

12.9

Usage Notes ...................................................................................................................... 592

12.9.1

Module Stop State Setting ................................................................................ 592

12.9.2

On-Chip RAM .................................................................................................. 592

12.9.3

DMAC Transfer End Interrupt.......................................................................... 592

12.9.4

DTCE Bit Setting.............................................................................................. 592

12.9.5

Chain Transfer .................................................................................................. 593

12.9.6

Transfer Information Start Address, Source Address, and Destination

Address ............................................................................................................. 593

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