H8SXSLASH1663M datasheet(424/1504 Pages) RENESAS

424 / 1504 page

Section 10 DMA Controller (DMAC)

Rev. 2.00 Sep. 24, 2008 Page 392 of 1468

REJ09B0412-0200

Bit

Bit Name

Initial

Value

R/W

Description

DTF1

DTF0

R/W

Data Transfer Factor 1 and 0

Select a DMAC activation source. When the on-chip

peripheral module setting is selected, the interrupt

source should be selected by DMRSR. When the

external request setting is selected, the sampling

method should be selected by the DREQS bit.

00: Auto request (cycle stealing)

01: Auto request (burst access)

10: On-chip module interrupt

11: External request

DTA

R/W

Data Transfer Acknowledge

This bit is valid in DMA transfer by the on-chip module

interrupt source. This bit enables or disables to clear the

source flag selected by DMRSR.

0: To clear the source in DMA transfer is disabled.

Since the on-chip module interrupt source is not

cleared in DMA transfer, it should be cleared by the

CPU or DTC transfer.

1: To clear the source in DMA transfer is enabled.

Since the on-chip module interrupt source is cleared

in DMA transfer, it does not require an interrupt by the

CPU or DTC transfer.

4, 3



All 0

Reserved

These bits are always read as 0 and cannot be

modified.

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