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H8SX/1663M データシート(PDF) 465 Page - Renesas Technology Corp

部品番号 H8SX/1663M
部品情報  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663M データシート(HTML) 465 Page - Renesas Technology Corp

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Section 10 DMA Controller (DMAC)
Rev. 2.00 Sep. 24, 2008 Page 433 of 1468
REJ09B0412-0200
(3)
Block Transfer Mode
In block transfer mode, the bus is released every time a 1-block size of transfers at a single transfer
request is completed.
In figure 10.28, the
TEND signal output is enabled and data is transferred in words from the
external 16-bit 2-state access space to the external 16-bit 2-state access space in block transfer
mode.
DMA read
cycle
DMA read
cycle
DMA write
cycle
Address bus
DMA write
cycle
DMA read
cycle
DMA read
cycle
DMA write
cycle
DMA write
cycle
B
φ
RD
LHWR, LLWR
TEND
Bus
released
Bus
released
Bus
released
Last block transfer cycle
Block transfer
Figure 10.28 Example of Transfer in Block Transfer Mode



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