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H8SX/1663M データシート(PDF) 553 Page - Renesas Technology Corp |
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H8SX/1663M データシート(HTML) 553 Page - Renesas Technology Corp |
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553 / 1504 page  Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Sep. 24, 2008 Page 521 of 1468 REJ09B0412-0200 B φ EDACK Bus cycle ETEND CPU cycle EXDMA single transfer cycle EXDMA single transfer cycle EXDMA single transfer cycle External space External space External space External space CPU cycle CPU cycle CPU cycle One bus cycle Last transfer cycle CPU operation Figure 11.40 Auto-Request/Normal Transfer Mode/Cycle Steal Mode (CPU Cycles/Single Address Mode) (2) Auto-Request/Normal Transfer Mode/Burst Mode With auto-request (in burst mode), when the DTE bit is set to 1 in EDMDR, an EXDMA transfer cycle is started a minimum of three cycles later. Once transfer is started, it continues (as a burst) until the transfer end condition is satisfied. Transfer requests for other channels are held pending until the end of transfer on the current channel. Figures 11.41 to 11.43 show operation timing examples for various conditions. CPU cycle CPU cycle CPU cycle EXDMAC read EXDMAC write EXDMAC read EXDMAC write EXDMAC read EXDMAC write Repeated External space External space External space 1 B φ Bus cycle CPU operation ETEND DTE bit Last transfer cycle 0 Figure 11.41 Auto-Request/Normal Transfer Mode/Burst Mode (CPU Cycles/Dual Address Mode) |
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