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H8SX/1663M データシート(PDF) 865 Page - Renesas Technology Corp |
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H8SX/1663M データシート(HTML) 865 Page - Renesas Technology Corp |
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865 / 1504 page  Section 16 8-Bit Timers (TMR) Rev. 2.00 Sep. 24, 2008 Page 833 of 1468 REJ09B0412-0200 16.5 Operation Timing 16.5.1 TCNT Count Timing Figure 16.7 shows the TCNT count timing for internal clock input. Figure 16.8 shows the TCNT count timing for external clock input. Note that the external clock pulse width must be at least 1.5 states for increment at a single edge, and at least 2.5 states for increment at both edges. The counter will not increment correctly if the pulse width is less than these values. P φ Internal clock TCNT input clock TCNT N – 1 N N + 1 Figure 16.7 Count Timing for Internal Clock Input P φ External clock input pin TCNT input clock TCNT N – 1 N N + 1 Figure 16.8 Count Timing for External Clock Input |
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