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H8SX/1663M データシート(PDF) 106 Page - Renesas Technology Corp |
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H8SX/1663M データシート(HTML) 106 Page - Renesas Technology Corp |
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106 / 1504 page ![]() Section 2 CPU Rev. 2.00 Sep. 24, 2008 Page 74 of 1468 REJ09B0412-0200 Table 2.14 Effective Address Calculation for Transfer and Operation Instructions 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 15 31 15 0 31 0 31 0 0 31 15 0 31 0 1, 2, or 4 31 31 0 0 31 0 31 1, 2, or 4 1, 2, or 4 31 0 7 No. op op rm rn IMM 1 2 3 4 5 6 7 op r op disp disp disp disp aa aa aa disp r op disp r op aa op disp r op disp r op aa op r op r op aa 31 0 0 1, 2, or 4 Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Immediate Register direct Register indirect Register indirect with 16-bit displacement Register indirect with 32-bit displacement Index register indirect with 16-bit displacement Index register indirect with 32-bit displacement Register indirect with post-increment or post-decrement Register indirect with pre-increment or pre-decrement 8-bit absolute address 16-bit absolute address 32-bit absolute address Sign extension SBR General register contents General register contents Zero extension Contents of general register (RL, R, or ER) Zero extension Contents of general register (RL, R, or ER) Sign extension General register contents General register contents General register contents Sign extension + ± × + + ± × + |
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