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H8SX/1663M データシート(PDF) 1074 Page - Renesas Technology Corp

部品番号 H8SX/1663M
部品情報  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663M データシート(HTML) 1074 Page - Renesas Technology Corp

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Section 21 I
2C Bus Interface 2 (IIC2)
Rev. 2.00 Sep. 24, 2008 Page 1042 of 1468
REJ09B0412-0200
Bit
Bit Name
Initial
Value
R/W
Description
2
1
0
BC2
BC1
BC0
0
0
0
R/W
R/W
R/W
Bit Counter 2 to 0
These bits specify the number of bits to be transferred
next. The settings of these bits should be made during
intervals between transfer frames. When setting these
bits to a value other than 000, the setting should be
made while the SCL line is low. The value return to 000
automatically at the end of a data transfer including the
acknowledge bit.
000: 9
001: 2
010: 3
011: 4
100: 5
101: 6
110: 7
111: 8
21.3.4
I
2C Bus Interrupt Enable Register (ICIER)
ICIER enables or disables interrupt sources and the acknowledge bits, sets the acknowledge bits to
be transferred, and confirms the acknowledge bit to be received.
Bit
Bit Name
Initial Value
R/W
7
TIE
0
R/W
6
TEIE
0
R/W
5
RIE
0
R/W
4
NAKIE
0
R/W
3
STIE
0
R/W
2
ACKE
0
R/W
1
ACKBR
0
R
0
ACKBT
0
R/W



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