H8SXSLASH1663M datasheet(1264/1504 Pages) RENESAS

1264 / 1504 page

Section 27 Clock Pulse Generator

Rev. 2.00 Sep. 24, 2008 Page 1232 of 1468

REJ09B0412-0200

External

clock

One cycle (worst case)

after the bus cycle completion

Operating clock

specified in SCKCR

Operating clock changed

CPU

Bus master

Figure 27.9 Clock Modification Timing

27.6.2

Notes on Resonator

Since various characteristics related to the resonator are closely linked to the user's board design,

thorough evaluation is necessary on the user's part, using the resonator connection examples

shown in this section as a reference. As the parameters for the resonator will depend on the

floating capacitance of the resonator and the mounting circuit, the parameters should be

determined in consultation with the resonator manufacturer. The design must ensure that a voltage

exceeding the maximum rating is not applied to the resonator pin.

27.6.3

Notes on Board Design

When using the crystal resonator, place the crystal resonator and its load capacitors as close to the

XTAL and EXTAL pins as possible. Other signal lines should be routed away from the oscillation

circuit as shown in Figure 27.10 to prevent induction from interfering with correct oscillation.

CL2

Signal A Signal B

CL1

This LSI

XTAL

EXTAL

Inhibited

Figure 27.10 Note on Board Design for Oscillation Circuit

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