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PC87309VLJ データシート(PDF) 32 Page - National Semiconductor (TI) |
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PC87309VLJ データシート(HTML) 32 Page - National Semiconductor (TI) |
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32 / 192 page  Configuration 32 www.national.com 2.8 SUPERI/O UART1 CONFIGURATION REGISTER (LOGICAL DEVICE 3) This read/write register is reset by hardware to 02h. Its bits function like the bits in the SuperI/O UART2 Configuration register 2.9 SUPERI/O KBC CONFIGURATION REGISTER (LOGICAL DEVICE 6) This read/write register is reset by hardware to 40h. Bit 0 - TRI-STATE Control When set, it causes the KBC pins (including the mouse clock and mouse data, but excluding DMA and IRQ), to be in TRI-STATE when the KBC is inactive (disabled). Bits 5-1 - Reserved Bits 7,6 - KBC Clock Source Bit 6 is the LSB. The clock source can be changed only when the KBC is inactive (disabled). 00: 8 MHz 01: 12 MHz 10: 16 MHz. 11: Reserved. 2.10 CONFIGURATION REGISTER BITMAPS TRI-STATE Control for Bank Select Enable 76543210 Reset Required 0 1 0 0 0 0 0 0 Index F0h Configuration Register, SuperI/O UART1 Power Mode Control Busy Indicator Reserved UART1 Pins Reserved KBC Clock Source 76543210 Reset Required 0 0 0 0 0 0 1 0 SuperI/O KBC Index F0h Configuration Register, TRI-STATE Control 76543210 Reset Required 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 SID Index 20h Register, Chip ID General Purpose Scratch Bits 76543210 Reset Required 0 x 1 0 x 0 0 0 SuperI/O Configuration 1 Index 21h BADDR0 PC-AT or PS/2 Drive Mode Select BADDR1 CFG0 Lock Scratch Bit KBC-Lock Register (SIOCF1), 76543210 Reset Required 0 0 0 0 0 0 0 0 SuperI/O Configuration 2 Index 22h Register (SIOCF2), MTR0/DRATE0 Select MTR1/P12 Select DR0,1 Function DR1/DENSEL Select IRRX1/P12/DRATE0 Select IRTX/DENSEL Select Reserved 76543210 Reset Required x x x x x x x x SRID Index 27h Register, Chip Revision ID |
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