PC87309VLJ datasheet(42/192 Pages) NSC

42 / 192 page

The Floppy Disk Controller (FDC) (Logical Device 0)

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3.3.5

Main Status Register (MSR)

This read-only register indicates the current status of the

Floppy Disk Controller (FDC), indicates when the disk con-

troller is ready to send or receive data through the Data

Data Register (FIFO).

The MSR can be read at any time. It should be read before

each byte is transferred to or from the Data Register (FIFO)

except during a DMA transfer. No delay is required when

reading this register after a data transfer.

The microprocessor can read the MSR immediately after a

hardware or software reset, or recovery from a power down.

The MSR contains a value of 00h, until the FDC clock has

stabilized and the internal registers have been initialized.

When the FDC is ready to receive a new command, it re-

ports a value of 80h for the MSR to the microprocessor.

System software can poll the MSR until the MSR is ready.

The MSR must report an 80h value (RQM set to 1) within

2.5 msec after reset or power up.

Bit 0 - Drive 0 Busy

This bit indicates whether or not drive 0 is busy.

It is set to 1 after the last byte of the command phase of

a SEEK or RECALIBRATE command is issued for drive

This bit is cleared to 0 after the first byte in the result

phase of the SENSE INTERRUPT command is read for

drive 0.

0: Not busy.

1: Busy.

Bit 1 - Drive 1 Busy

This bit indicates whether or not drive 1 is busy.

It is set to 1 after the last byte of the command phase of

a SEEK or RECALIBRATE command is issued for drive

This bit is cleared to 0 after the first byte in the result

phase of the SENSE INTERRUPT command is read for

drive 1.

0: Not busy.

1: Busy.

Bit 2 - Drive 2 Busy

This bit indicates whether or not drive 2 is busy.

It is set to 1 after the last byte of the command phase

of a SEEK or RECALIBRATE command is issued for

drive 2.

This bit is cleared to 0 after the first byte in the result

phase of the SENSE INTERRUPT command is read for

drive 2.

0: Not busy.

1: Busy.

Bit 3 - Drive 3 Busy

This bit indicates whether or not drive 3 is busy.

It is set to 1 after the last byte of the command phase

of a SEEK or RECALIBRATE command is issued for

drive 3.

This bit is cleared to 0 after the first byte in the result

phase of the SENSE INTERRUPT command is read for

drive 3.

0: Not busy.

1: Busy.

Bit 4 - Command in Progress

This bit indicates whether or not a command is in

progress. It is set after the first byte of the command

phase is written. This bit is cleared after the last byte of

the result phase is read.

If there is no result phase in a command, the bit is

cleared after the last byte of the command phase is

written.

0: No command is in progress.

1: A command is in progress.

Bit 5 - Non-DMA Execution

This bit indicates whether or not the controller is in the

execution phase of a byte transfer operation in non-

DMA mode.

This bit is used for multiple byte transfers by the micro-

processor in the execution phase through interrupts or

software polling.

0: The FDC is not in the execution phase.

1: The FDC is in the execution phase.

Bit 6 - Data I/O (Direction)

Indicates whether the controller is expecting a byte to be

written or read, to or from the Data Register (FIFO).

0: Data will be written to the FIFO.

1: Data will be read from the FIFO.

Bit 7 - Request for Master (RQM)

This bit indicates whether or not the controller is ready

to send or receive data from the microprocessor through

the Data Register (FIFO). It is cleared to 0 immediately

after a byte transfer and is set to 1 again as soon as the

disk controller is ready for the next byte.

During a Non-DMA execution phase, this bit indicates

the status of the interrupt.

0: Not ready. (Default)

1: Ready to transfer data.

76543210

Reset

Required

Main Status

Offset 04h

Drive 2 Busy

Non-DMA Execution

Data I/O Direction

RQM

Drive 1 Busy

Drive 3 Busy

Command in Progress

Drive 0 Busy

Read Operations

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