PC87309VLJ datasheet(80/192 Pages) NSC

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Parallel Port (Logical Device 1)

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TABLE 4-1. Parallel Port Mode Selection

1. Section 2.6 "SUPERI/O PARALLEL PORT CONFIGURATION REGISTER (LOGICAL DEVICE 1)" on page 30

describes the bits of the SuperI/O Parallel Port conﬁguration register.

2. See Section 4.5.12 "Extended Control Register (ECR)" on page 91

3. Before modifying this bit, set bit 4 of the SuperI/O Parallel Port conﬁguration register at index F0h to 1.

4. Use bit 7 of the Control2 register at second level offset 2 of the parallel port to further specify compatibility. See

Section 4.5.17 "Control2 Register" on page 93.

TABLE 4-2. Parallel Port Reset States

4.2.1

SPP Modes Register Set

In all Standard Parallel Port (SPP) modes, port operation is

controlled by the registers listed in TABLE 4-3 "Standard

Parallel Port (SPP) Registers".

All register bit assignments are compatible with the assign-

ments in existing SPP devices.

A single Data Register DTR is used for data input and out-

put (see Section 4.2.2 "SPP Data Register (DTR)"). The di-

rection of data flow is determined by the system setting in

bit 5 of the Control Register CTR.

TABLE 4-3. Standard Parallel Port (SPP) Registers

4.2.2

SPP Data Register (DTR)

This bidirectional data port transfers 8-bit data in the direc-

tion determined by bit 5 of SPP register CTR at offset 02h

and mode.

The read or write operation is activated by the system RD

and WR strobes.

TABLE 4-4 "SPP DTR Register Read and Write Modes"

tabulates DTR register operation.

TABLE 4-4. SPP DTR Register Read and Write Modes

In SPP Compatible mode, the parallel port does not write

data to the output signals. Bit 5 of the CTR register has no

effect in this state. If data is written (WR goes low), the data

is sent to the output signals PD7-0. If a read cycle is initiated

(RD goes low), the system reads the contents of the output

latch, and not data from the PD7-0 output signals.

In SPP Extended mode, the parallel port can read and write

external data via PD7-0. In this mode, bit 5 sets the direction

for data in or data out, while read or write cycles are possi-

ble in both settings of bit 5.

Conﬁguration

Time

Operation Mode

SuperI/O Parallel Port

Conﬁguration Register

(Index F0h)1

Extended Control Register

(ECR) of the Parallel Port

(Offset 402h) 2

Control2 Register

of the Parallel Port

(Offset 02h) 3

7 6 5

Conﬁguration at

System Initial-

ization

(Static)

SPP Compatible

0 0 0

SPP Extended

0 0 1

EPP Revision 1.7

0 1 0

EPP Revision 1.9

0 1 1

Conﬁguration at

System Initial-

ization with

Run-Time Re-

conﬁguration

(Dynamic)

SPP Compatible

1 0 0

1 1 1

0 0 0

PP FIFO

0 1 0

SPP Extended

0 0 1

EPP Revision 1.7

1 1 1

1 0 0

EPP Revision 1.9

ECP(Default)

1 0 0

1 1 1

0 1 1

Signal

Reset Control

State After Reset

SLIN

TRI-STATE

INIT

Zero

AFD

TRI-STATE

STB

TRI-STATE

IRQ5,7

TRI-STATE

Offset

Name

Description

R/W

00h

DTR

Data

R/W

01h

STR

Status

02h

CTR

Control

R/W

03h

TRI-STATE

Mode

Bit 5 of

CTR

RD WR

Result

SPP Com-

patible

Data written to PD7-0.

Data read from the out-

put latch

SPP Ex-

tended

Data written to PD7-0.

Data written is latched

Data read from output

latch.

Data read from PD7-0.

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